This invention relates to a method and apparatus for measuring propagation delays of integrated circuit devices. Such delay measurements are useful for integrated circuit manufacturing process characterization and qualification, and for designing large scale integrated circuits.
Very high speed large scale integrated circuit (IC) applications have revealed a definite need for assessing circuit and device parameters of importance for high speed digital circuit designs. The data obtained from high speed test circuits, in conjunction with validated circuit models, can help the IC designer make the proper decisions in achieving design goals. The problem is to obtain data that characterizes propagation delays through the stages (gates, inverters or the like) that are to be used in the digital circuit designs.
In the past, propagation delay measurements have been made using an integrated circuit ring oscillator having many stages, the operating frequency of which is determined as a measure of propagation delay through the stages. Dividing the oscillation period by twice the number of stages furnishes an average delay propagation through one stage. This method has certain disadvantages. Because propagation delays are inherently very short for each stage, a very large number of stages is required in order to have an easily measured oscillation period. Such a large number of stages requires too much space on an integrated circuit chip. A more serious problem is that the oscillator is subject to having spurious harmonic modes of oscillation. It is desirable to measure gate propagation delays directly, without having to use oscillations, and thus be free from effects caused by such feedback and coupling.